Layers of metals and metal oxides, particularly the heavier elements of Group VIII, are becoming important for a variety of electronic and electrochemical applications. For example, high quality RuO2 thin films deposited on silicon wafers have recently gained interest for use in ferroelectric memories. Many of the Group VIII metal layers are generally unreactive toward silicon and metal oxides, resistant to diffusion of oxygen and silicon, and are good conductors. Oxides of certain of these metals also possess these properties, although perhaps to a different extent.
Thus, layers of Group VIII metals and metal oxides, particularly the second and third row metals (e.g., Ru, Os, Rh, Ir, Pd, and Pt) have suitable properties for a variety of uses in integrated circuits. For example, they can be used in integrated circuits for electrical contacts. They are particularly suitable for use as barrier layers between the dielectric material and the silicon substrate in memory devices, such as ferroelectric memories. Furthermore, they may even be suitable as the plate (i.e., electrode) itself in capacitors. Rhodium is of particular interest because it is one of a few elements having a resistivity of less than 5 μΩ-cm (resistivity at 20° C.=4.51 μΩ-cm).
Capacitors are used in a wide variety of integrated circuits. Capacitors are of special concern in DRAM (dynamic random access memory) circuits; therefore, the invention will be discussed in connection with DRAM memory circuits. However, the invention has broader applicability and is not limited to DRAM memory circuits. It may be used in other types of memory circuits, such as SRAMs, as well as any other circuit in which cell dielectrics are used.
There is continuous pressure in the industry to decrease the size of individual cells and increase memory cell density to allow more memory to be squeezed onto a single memory chip. However, it is necessary to maintain a sufficiently high storage capacitance to maintain a charge at the refresh rates currently in use even as cell size continues to shrink. This requirement has led DRAM manufacturers to turn to three dimensional capacitor designs, including trench and stacked capacitors. Stacked capacitors are capacitors which are formed over the access transistor in a semiconductor device. In contrast, trench capacitors are formed in the wafer substrate beneath the transistor. For reasons including ease of fabrication and increased capacitance, most manufacturers of DRAMs larger than 4 Megabits use stacked capacitors. Therefore, the present invention will be discussed in connection with stacked capacitors, but should not be understood to be limited thereto.
One widely used type of stacked capacitor is known as a container capacitor. Known container capacitors are in the shape of an upstanding tube (cylinder) with an oval or circular cross section. The wall of the tube consists of two electrodes, i.e., two plates of conductive material, such as doped polycrystalline silicon (referred to herein as polysilicon or poly), separated by a dielectric, such as tantalum pentoxide (Ta2O5). The bottom end of the tube is closed, with the outer wall in contact with either the drain of the access transistor or a plug which itself is in contact with the drain. The other end of the tube is open. The sidewall and closed end of the tube form a container; hence the name “container capacitor.”
The electrodes in a DRAM cell capacitor must protect the dielectric layer from interaction with surrounding materials, including interlayer dielectrics (e.g., BPSG), and from the harsh thermal processing encountered in subsequent steps of DRAM process flow. In order to function well as a bottom electrode, the electrode layer or layer stack must act as an effective barrier to the diffusion of oxygen and silicon. Oxidation of the underlying Si will result in decreased series capacitance, thus degrading the cell capacitor. Platinum is one of the candidates for use as an electrode material for high dielectric capacitors. Platinum, alone, however, is relatively permeable to oxygen. One solution is to alloy the Pt with Rh to enhance the barrier properties of the layer. Physical vapor deposition (PVD) of a Pt—Rh alloy has been shown by H. D. Bhatt et. al., “Novel high temperature multi-layer electrode barrier structure for high-density ferroelectric memories,” Applied Physics Letters, 71, pp. 719-21 (1997), to provide an improvement over pure Pt for electrode applications. However, PVD deposition does not deliver a layer which is sufficiently conformal for VLSI devices.
Thus, there is a continuing need for methods and materials for the deposition of metal-containing layers, such as rhodium-containing layers, which can function as barrier layers, for example, in integrated circuits. Furthermore, what is needed are capacitor electrodes, barrier layers, and fabrication methods that offer a combination of good conformality, high conductivity, and good barrier properties.